1. Field of the Invention
The present invention relates to a method for decoding a data sequence which consists of K information bits and has been encoded with the aid of a binary convolutional code, using a MaxLogMAP algorithm.
2. Description of the Related Art
Voice channels and data channels of a radio communications system, which is designed to operate to the GSM/EDGE mobile radio communications standard for example, use binary convolutional codes for data coding and data decoding. A preferred algorithm for what is known as “soft input/soft output decoding” is the known “symbol-by-symbol log-likelihood maximum a posteriori probability” algorithm (LogMAP algorithm), which is generally implemented with the aid of a maximum approximation (MaxLogMAP algorithm).
The basic MAP algorithm is described, for example, in the publication “Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate”, L. R. Bahl et al., IEEE Transactions on Information Theory, pp. 284–287, March 1974. The MaxLogMAP algorithm can be found in the publication “Iterative Decoding of Binary Block and Convolutional Codes”, J. Hagenauer et al., IEEE Transactions on Information Theory, vol. 42, no. 2, pp. 429–445, March 1996.
A window MaxLogMAP algorithm implemented with the aid of what is known as a “sliding window” (decoding window) is described in the publication “An Intuitive Justification and a Simplified Implementation of the MAP Decoder for Convolutional Codes”, A. J. Viterbi, IEEE Journal on Selected Areas in Communications, vol. 16, no.2, pp. 260–264, February 1998.
The basis for decoding a data sequence encoded with the aid of a binary convolutional code is the binary trellis diagram. One segment of the trellis diagram belonging to one information bit of the data sequence detects all possible combinations of m (convolutional code memory length) preceded information bits as 2m initial states. Furthermore, all ensuing “conversions” (codings) of the information bit are detected as 2(m+1) state transitions, and resulting 2m target states are detected as initial states for the next consecutive information bit. Here an information bit sequence corresponds to a specific path within the trellis diagram, a sequence of the most probable information bits in the trellis diagram being established with the aid of the MaxLogMAP algorithm.
When the MaxLogMAP algorithm is implemented, a distinction essentially has to be made between a systolic implementation and a processor-oriented implementation.
With the systolic implementation the aim is to achieve as high a degree of parallelism as possible of decoding steps throughout the trellis diagram. This implementation is used with extremely high data throughput requirements of up to 50 Gbit/s.
Processor-oriented implementation is suitable for moderate data throughput requirements of a few Mbit/s using low-cost hardware.
For both implementations it is assumed that, for large data sequences transmitted block-by-block, decoding can be usefully implemented only with the aid of a decoding window.
For reasons of data throughput and hardware cost the window MaxLogMAP algorithm is generally used for decoding.
Decoding results (soft output values) which are, by way of comparison, obtained using a MaxLogMAP algorithm without a decoding window may be more precise, but expensive hardware and memories are required for this purpose.
An alternative to the MaxLogMAP algorithm, based on a block error probability with a given signal-to-noise ratio, is provided by the “soft output Viterbi algorithm” (SOVA) described in DE 39 10 739 C3 and DE 42 24 214 C2. However, the SOVA algorithm has a smaller correlation between decoding errors and soft output values formed than the MaxLogMAP algorithm.